1. Field of the Invention
The present invention relates generally to semiconductors and more specifically to devices comprising a plurality of gates that have been processed through to the second metal deposition and are thereafter customized with the aid of specialized computer placement and routing software for a particular application in one step by a single customized etch of the second metal pattern, or in two steps by a first standard pattern etch followed a second custom pattern etch of the second metal.
2. Description of the Prior Art
The advantages of high density integrated circuit technology were initially unavailable for use in designs that had low production runs. The initial engineering costs of a fully custom chip were too much to amortize over low volumes of devices. Huge manufacturing batches of thousands and tens of thousands of chips sharing one design were needed to realize scales of economies that are the hallmark of modern semiconductor processing.
The introduction of application specific integrated circuits (ASICs) and gate arrays lowered the number of devices a single design had to produce to be economical. This was accomplished by standardizing cells of transistors and logic gates and constraining users to define the required interconnections necessary to realize the desired functionality. Schematic capture and Boolean algebra software front-ends have emerged to make the placement and routing easier for a user to specify and whole functions, such as shift registers, UARTs, and CPUs are now available as cell libraries for use in a user's automatic placement and routing of a custom design.
Zvi Orbach, et al., describe in U.S. Pat. No. 4,875,971, issued Oct. 24, 1989, a technique for production of customized integrated circuits from finished blanks where portions of the metal conductors are removed at a plurality of metal layers in the finished blank using a single mask. Metal I and metal II layers are generally arranged in mutually perpendicular orientation so as to define a grid. Vias interconnect the metal layers and contact layer, and an insulating layer separates them all. A passivation layer is formed over the metal II layer. The metal I and metal II layers are such that they are always exposed for etching at locations where removal thereof may be desired. For customization, a photoresist layer is deposited over the passivation layer such that an application specific mask may be used to expose the photoresist layer. The application specific mask defines locations at which metal is to be removed from either the metal I layer or the metal II layer.
Zvi Orbach describes in U.S. Pat. No. 4,924,287, issued May 8, 1990, an integrated circuit including transistors and fusible links interconnecting the transistors such that selective fusing of the links can define an electronic function. Groups of transistors and links are definable into cells which include logic functions (e.g. gates, flip-flops and registers) and analog functions (e.g. op-amps and analog switches). The fusible links are expressly not electrically programmable, but rather are cut by an apparatus that scans the surface of the device and directs on the surface "a source of fusing energy." This energy would typically be a laser beam energetic enough to cut through the metal.
Zvi Orbach, et al., describe in U.S. Pat. No. 4,933,738, issued Jun. 12, 1990, a selectably customizable semiconductor device having first and second metal layers disposed in two different planes and include elongated strips with conductive branches. Metal I is formed into strips that lie in an "east-west" orientation and metal II is formed into strips that lie orthogonal to metal I strips in a "north-south" orientation. A sharing of vias is possible and an advantage of enhanced compactness is claimed thereby. Fuse links for device customization are provided on branch strips.
Zvi Orbach, et al., describe in U.S. Pat. No. 4,960,729, issued Oct. 2, 1990, a technique for providing radiation formable conductive link (antifuse) in an integrated circuit. Aluminum and amorphous silicon form the basic antifuse link. A laser radiation diffuses the aluminum into the amorphous silicon forming a highly conductive aluminum doped silicon bridge. Antifuse links act as vias between metal I and metal II layers and therefore can be programmed to configure various circuit functions.
Zvi Orbach, et al., describe in U.S. Pat. No. 5,049,969, issued Sep. 17, 1991, a selectably customizable semiconductor device including a first and second metal layers disposed in parallel planes. Each metal layer comprises elongated strips orthogonal to one another in their respective planes. Fusible conductive bridges join adjacent pairs of strips in one plane. Branch strips connect one of the fusible conductive bridges at locations intermediate to first and second fusible links. Laser cutting is employed to etch some of the fusible links. All of the fusible links are formed on the second metal layer. As such, no holes in the insulating layer are used such that personalization of a device does not require a change in the fabrication process.
Zvi Orbach, et al., describe in U.S. Pat. No. 5,111,273, issued May 5, 1992, an integrated circuit that has an insulation layer disposed over a collection of semiconductor elements, such as transistors formed on a silicon substrate, with discrete apertures overlying fusible links. Predetermined combinations of the fusible links are fused to produce particular functions from the combinations of the semiconductor elements. The fusible links include a first group that make connections between individual semiconductor elements to define functional groups, and a second group that provide a plurality of connections among the functional groups. The fusible links are fused by "application of energy locally to the links themselves . . . ". A Florod Corporation laser cutter is described in one example. No electrical connections are provided for fusing, which "greatly simplifies the design and increases the circuit carrying capacity of integrated circuits."